Archive for May, 2015


Computer Organization & Architecture – Designing for Performance….

May 31, 2015

computer organization - designing for performance

For my first introduction , just borrowed a book from National Library (PNM) entitled Computer Organization & Architecture – Designing for Performance written by William Stallings. This book mainly tell us about the computer architecture , the CPU , memory , processor , I/O devices , the control unit  and parallel organization. It tells us about how computers are organized  and made of , the definitions of a computer system , the Pentium Family Processor and PowerPC and so on…The memory of the computer system – the cache memory , DDR SDRAM memory are also discussed in this book.

RAM technology is divided into two technologies: dynamic and static. A dynamic RAM (DRAM) is made with cells that store data as charge on capacitors. The presence or absence of charge in a capacitor is interpreted as a binary 1 or 0. Because capacitors have a naturaltendency to discharge , dynamic RAMs require periodic charge refreshing to maintain data storage. The term dynamic refers to this tendency of the stored charge to leak away , even with power continuously applied.

When only a small number of ROMs with a particular memory content is needed , a less expensive  alternative is the programmable ROM (PROM). Like the ROM , the PROM is nonvolatile and may be written into only once. For the PROM , the writing process is performed electrically and may be performed by a supplier or customer at a time later than the original chip fabrication. Special equipment is required for the writing or “programming” process. PROMs provide flexibility and convenience. The ROM remains attractive for high-volume production runs.

In a typical DRAM , the processor presents addresses and control levels to the memory , indicating that a set of data at a particular location in memory should be either read from or written into the DRAM. After a delay , the access time , the DRAM either writes or reads the data. During the access-time delay , the DRAM performs various internal functions , such as activating the high capacitance of the row and column lines , sensing the data , and routing the data out through the output buffers. The processor must simply wait through this delay , slowing performance.

With the synchronous access , the DRAM moves data in and out under control of the system clock. The processor or other master issues the instruction and address information , which is latched by the DRAM. The DRAM then responds after a set of number of clock cycles. Meanwhile , the master can safely do other tasks while the SDRAM is processing the request.

InfiniBand is a recent I/O specification aimed at the high-end server market. The first version of the specification was released in early 2001 and has attracted numerous vendors. The standard describes an architecture and specifications for data flow between processors and intelligent I/O devices. InfiniBand is intended to replace the PCI bus in servers , to provide greater capacity , increased expandability , and enhanced flexibility in server design. In essence , InfiniBand enables servers , remote storage, and other network devices to be attached in a central fabric or switches and links. The switch-based architecture can connect up to 64,000 servers , storage systems , and networking devices.

The Pentium Processor – Register Organization – The register organization includes the following type of registers:

1. General: There are eight 32 bit general purpose registers. These may be used for all types of Pentium instructions; they can also hold operands for address calculations. In addition , some of these registers also serve special purposes. For example , string instructions use the contents of the ECX , ESI , and EDI registers operands without having to reference these registers explicitly in the instruction. As a result , a number of instructions can be encoded more compactly.

2. Segment: The 16-bit segment registers contain segment selectors , which index into segment tables. The code segment (CS) register references the segment containing the instruction being executed, The stack segment (SS) register references the segment containing a user-visible stack. The remaining segment registers (DS,ES,FS,GS) enable the user to reference up to four separate data segments at a time.

* The rest you can find at page 442 Chapter 12 (Processor Structure and Function).

In conclusion , this book is a great book to read if you want to know about the computer architecture and organization , starting from the 80386 to Pentium 4  processor. For parallel organization or parallel processing , you can check it out at page 637 and 638 of the book. Stallings provides a clear, comprehensive presentation of the organization and architecture of modern-day computers, emphasizing both fundamental principles and the critical role of performance in driving computer design. The text conveys concepts through a wealth of concrete examples highlighting modern CISC and RISC systems.

p/s:- Some of the excerpt are taken from this book – Computer Organization & Architecture – Designing for Performance – 7th Edition –  written by William Stallings , published by Pearson Prentice Hall.